The utility of a program controlled processor is related to the number and type of instructions which are used to control the various circuits of the processor. Each type of processor, for example a microprocessor, includes a finite number of instructions, each of which can be used in a program to control the microprocessor circuits to accomplish a desired task. Microprocessor instruction sets typically include instructions in the nature of fetch, move data, compare, add, subtract, etc.
Each of the instructions comprising an instruction set must be decoded by the microprocessor into binary signals recognized by the processing circuitry to carry out the specific function. More commonly, the microprocessor decodes each instruction into a unique entry point address to a microcode memory which is the starting point for carrying out the specific function. In essence, the entry point address for each instruction is the starting point of a sequence of subsequent memory read and write operations which yield output data and electrical signals directed to arithmetic logic units and other registers. The overall end result is the accomplishment of the function defined by the instruction. The microcode memory is generally in the nature of a Read Only Memory (ROM) preprogrammed so as to be responsive to each instruction of the entire set for providing the necessary output data and signals. In progressing through the concatenation of operations, various addressed memory locations have stored therein data representative of other addresses with which the memory must be addressed to yield data or yet other addresses for carrying out the desired function in accordance with the instructions.
As the microprocessor steps through instructions of the application program, each such program instruction is stored in an instruction register. A Programmable Logic Array (PLA) is conventionally employed to convert the binary bits stored in the instruction register to an address of the microcode ROM which is the entry point for that instruction. The PLA is configured or programmed to convert each instruction of the entire set into a different entry point address for the microcode ROM. The PLA is customarily programmed so that the entry points for the instructions are located adjacently in a small section of the microcode ROM.
While the conventional approach of using a PLA provides adequate decoding capabilities, the plural levels of logic contribute significantly to the overall delay in providing a decoded address for the microcode memory. In some cases, the PLA is provided with an output latch, in which event one processing clock cycle may be required to provide a decoded entry point address. This overall delay in the instruction pipeline must be encountered during the execution of each instruction. Also, because the decoding of column addresses of conventional ROMs is inherently slower than row address decoding, the delay in the instruction pipeline is affected accordingly. Self tests of microprocessors are employed many times to assure the integrity of the microcode memory contents. When PLAs are used as the instruction word binary bit converter, additional instruction word register hardware is necessary to provide the self tests, and multiple sequences are needed.
In view that the trend is toward the construction of faster processing equipment, it can be seen that a need has arisen for an instruction decoding technique which does not burden the processing system with excessive delay, with additional hardware for test sequences, or with an additional clock cycle. From the foregoing, there is also an associated need for an instruction decoder which accommodates various types of instruction formats without a substantial increase in the complexity of the circuit, nor a compromise in the decoding speed.